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| - 1 - m470t6464fbs rev. 1.2, oct. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" basis, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered trademarks belong to their respective owners. ? 2010 samsung electronics co., ltd. all rights reserved. datasheet m470t2863fb3 M470T2864FB3 m470t5663fb3 200pin unbuffered sodimm based on 1gb f-die 60fbga/84fbga with lead-free & halogen-free (rohs compliant) h t t p : / / w w w . b d t i c . c o m / s a m s u n g
- 2 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm revision history revision no. history draft date remark editor 1.0 - first release jun. 2010 - s.h.kim 1.1 - changed idd current spec : idd3ps jul. 2010 - s.h.kim 1.2 - added 512mb x16, 1gb x8 part no. oct. 2010 - s.h.kim h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 3 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm table of contents 200pin unbuffered sodimm based on 1gb f-die 1. ddr2 unbuffered sodimm ordering information ................................................................................. ....................... 4 2. key features................................................................................................................ ................................................. 4 3. address configuration ....................................................................................................... ........................................... 4 4. pin configurations (front side/back side)....... .............................................................................................................. 5 5. pin description............................................................................................................. ................................................. 5 6. input/output function description ..................... ........................................................................................................... 6 7. functional block diagram : .................................................................................................. ......................................... 7 7.1 512mb, 64mx64 module - m470t6464 fbs ............... .................................................. ............ ........... .................... 7 7.2 1gb, 128mx64 module - m470t2863f b3 ............... ..................................................... ............ ......... ...................... 8 7.3 1gb, 128mx64 module - m470t2864f b3 ............... ..................................................... ............ ......... ...................... 9 7.4 2gb, 256mx64 module - m470t5663f b3 ............... ..................................................... ............ ......... ...................... 10 8. absolute maximum dc ratings ... .............................................................................................. ................................... 11 9. ac & dc operating conditions................................................................................................ ..................................... 11 9.1 recommended dc operating conditions (sstl - 1.8).... ....................................................................... ................ 11 9.2 operating temperature condition ............................................................................................ ............................... 12 9.3 input dc logic level ....................................................................................................... ........................................ 12 9.4 input ac logic level ....................................................................................................... ........................................ 12 9.5 ac input test conditions................................................................................................... ...................................... 12 10. idd specification parameters definition ............. ....................................................................... ................................. 13 11. operating current table : .................................................................................................. ......................................... 14 11.1 m470t6464fbs : 64mx64 512mb module .............................................................................. .......... ................... 14 11.2 m470t2863fb3 : 128mx64 1gb modu le .............. ..................................................... ............ .......... ..................... 14 11.3 M470T2864FB3 : 128mx64 1gb modu le .............. ..................................................... ............ .......... ..................... 15 11.4 m470t5663fb3 : 256mx64 2gb modu le .............. ..................................................... ............ .......... ..................... 15 12. input/output capacitance ................................................................................................... ........................................ 16 13. electrical characteristics & ac timing for ddr2-800/ 667 ............. .......................................... ............. ..................... 16 13.1 refresh parameters by device density...................................................................................... ........................... 16 13.2 speed bins and cl, trcd, trp, trc and tras for corre sponding bin ....... ............................ ............ ........... ...... 16 13.3 timing parameters by speed grade ..................... ..................................................................... ........................... 17 14. physical dimensions : ................................... ................................................................... ........................................... 19 14.1 64mbx16 based 64mx64 module (1rank)................... ........................................................ ............ ...................... 19 14.2 128mbx8 based 128mx64 module (1rank).............. ........................................................................ ..................... 20 14.3 64mbx16 based 128mx64 module (2ranks) ............ ......................................................................... .................... 21 14.4 128mbx8 based 256mx64 module (2ranks) ............ ......................................................................... .................... 22 h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 4 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 1. ddr2 unbuffered sodimm ordering information note : 1. ?b? of part number(11th digit) stands for flip chip, lead-free, halogen-free and rohs compliant products. 2. ?3? of part number(12th digit) stands for dummy pad pcb products. 3. ?s? of part number(12th digit) stands for reduced layer pcb products. 2. key features ? performance range e7 (ddr2-800) f7 (ddr2-800) e6 (ddr2-667) unit speed@cl3 400 - 400 mbps speed@cl4 533 533 533 mbps speed@cl5 800 667 667 mbps speed@cl6 - 800 - mbps cl-trcd-trp 5-5-5 6-6-6 5-5-5 ck ? jedec standard v dd = 1.8v 0.1v power supply ?v ddq = 1.8v 0.1v ? 333mhz f ck for 667mb/sec/pin ? 4 banks ? posted cas ? programmable cas latency: 3, 4, 5, 6 ? programmable additive latency: 0, 1, 2, 3, 4, 5 ? write latency(wl) = read latency(rl) -1 ? burst length: 4 , 8(interleave/nibble sequential) ? programmable sequential / interleave burst mode ? bi-directional differential data-strobe (s ingle-ended dat a-strobe is an optional feature) ? off-chip driver(ocd) impedance adjustment ? on die termination with selectabl e values(50/75 /150 ohms or disable ) ? average refresh period 7.8us at lower than a t case 85c, 3.9us at 85 c < t case < 95 c - support high temperature self-refresh rate enable feature ? package: 60ball fbga - 128mx8 84ball fbga - 64mx16 ? all of base components are flip chip and rohs compliant note : for detailed ddr2 sdram operation, please refer to samsung?s device operation & timing diagram. 3. address configuration part number density organization component composition number of rank height m470t6464fbs-ce7/f7/e6 512mb 64mx64 64mx16(k4t1g164qf)*4 1 30mm m470t2863fb3-ce7/f7/e6 1gb 128mx64 128mx8(k4t1g084qf)*8 1 30mm M470T2864FB3-ce7/f7/e6 1gb 128mx64 64mx16(k4t1g164qf)*8 2 30mm m470t5663fb3-ce7/f7/e6 2gb 256mx64 128mx8(k4t1g084qf)*16 2 30mm organization row address column address bank address auto precharge 128mx8(1gb) based module a0-a13 a0-a9 ba0-ba1 a10 64mx16(1gb) based module a0-a12 a0-a9 ba0-ba1 a10 h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 5 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 4. pin configurations (front side/back side) note :nc = no connect; nc, test(pin 163)is for bus analysis tool and is not connected on normal memory modules. 5. pin description note : the v dd and v ddq pins are tied to the single power-plane on pcb. pin front pin back pin front pin back pin front pin back pin front pin back 1v ref 2v ss 51 dqs2 52 dm2 101 a1 102 a0 151 dq42 152 dq46 3v ss 4dq453v ss 54 v ss 103 v dd 104 v dd 153 dq43 154 dq47 5 dq0 6 dq5 55 dq18 56 dq22 105 a10/ap 106 ba1 155 v ss 156 v ss 7dq18 v ss 57 dq19 58 dq23 107 ba0 108 ras 157 dq48 158 dq52 9v ss 10 dm0 59 v ss 60 v ss 109 we 110 s 0 159 dq49 160 dq53 11 dqs 012 v ss 61 dq24 62 dq28 111 v dd 112 v dd 161 v ss 162 v ss 13 dqs0 14 dq6 63 dq25 64 dq29 113 cas 114 odt0 163 nc, test 164 ck1 15 v ss 16 dq7 65 v ss 66 v ss 115 nc/s 1 116 a13 165 v ss 166 ck 1 17 dq2 18 v ss 67 dm3 68 dqs 3117 v dd 118 v dd 167 dqs 6168 v ss 19 dq3 20 dq12 69 nc 70 dqs3 119 nc/odt1 120 nc 169 dqs6 170 dm6 21 v ss 22 dq13 71 v ss 72 v ss 121 v ss 122 v ss 171 v ss 172 v ss 23 dq8 24 v ss 73 dq26 74 dq30 123 dq32 124 dq36 173 dq50 174 dq54 25 dq9 26 dm1 75 dq27 76 dq31 125 dq33 126 dq37 175 dq51 176 dq55 27 v ss 28 v ss 77 v ss 78 v ss 127 v ss 128 v ss 177 v ss 178 v ss 29 dqs 1 30 ck0 79 cke0 80 nc/cke1 129 dqs 4 130 dm4 179 dq56 180 dq60 31 dqs1 32 ck 081v dd 82 v dd 131 dqs4 132 v ss 181 dq57 182 dq61 33 v ss 34 v ss 83 nc 84 nc 133 v ss 134 dq38 183 v ss 184 v ss 35 dq10 36 dq14 85 ba2 86 nc 135 dq34 136 dq39 185 dm7 186 dqs 7 37 dq11 38 dq15 87 v dd 88 v dd 137 dq35 138 v ss 187 v ss 188 dqs7 39 v ss 40 v ss 89 a12 90 a11 139 v ss 140 dq44 189 dq58 190 v ss 41 v ss 42 v ss 91 a9 92 a7 141 dq40 142 dq45 191 dq59 192 dq62 43 dq16 44 dq20 93 a8 94 a6 143 dq41 144 v ss 193 v ss 194 dq63 45 dq17 46 dq21 95 v dd 96 v dd 145 v ss 146 dqs 5 195 sda 196 v ss 47 v ss 48 v ss 97 a5 98 a4 147 dm5 148 dqs5 197 scl 198 sa0 49 dqs 2 50 nc 99 a3 100 a2 149 v ss 150 v ss 199 v ddspd 200 sa1 pin name description pin name description ck0,ck1 clock inputs, positive line sda spd data input/output ck 0,ck 1 clock inputs, negative line sa1,sa0 spd address cke0,cke1 clock enables dq0~dq63 data input/output ras row address strobe dm0~dm7 data masks cas column address strobe dqs0~dqs7 data strobes we write enable dqs 0~dqs 7 data strobes complement s 0,s 1c h i p s e l e c t s t e s t logic analyzer specific test pin (no connect on so-dimm) a0~a9, a11~a13 address inputs v dd core and i/o power a10/ap address input/autoprecharge v ss ground ba0,ba1 sdram bank address v ref input/output reference odt0,odt1 on-die termination control v ddspd spd power scl serial presence detect(spd) clock input nc spare pins, no connect ck0,ck1 clock inputs, positive line sda spd data input/output h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 6 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 6. input/output function description ck0-ck1 0- 1 cke0-cke1 input 0- 1 , , we input ba0~ba2 odt0~odt1 input a0~a9, a10/ap, a11~a13 input dq0~dq63 in/out dm0~dm7 input dqs 0~ dqs 7 in/out v dd ,v ddspd ,v ss supply sa0~sa1 input test in/out symbol type description ck ck input the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and falling edge of ck . a delay locked loop (dll) circuit is driven from the clock input and output timing for read operations is sy nchronized to the input clock. activates the ddr2 sdram ck signal when high and deacti vates the ck signal when low, by deactivating the clocks, cke low initiates the power down mode or the self refesh mode. s s input enables the associated ddr2 sdram command decod er when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s 0, rank 1 is selected by s 1. ranks are also called ?physical banks?. ras cas when sampled at the cross point of the rising edge of ck and falling edge of ck , cas , ras , and we define the operation to be executed by the sdram. input selects which ddr2 sdram internal bank is activated. asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr2 sdram extended mode register set (emrs). during a bank activate command cycle, defines the row address when sampl ed at the cross point of the ris- ing edge of ck and falling edge of ck. during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autopre- charge is disabled. during a precharge command cycle, ap is used in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be pecharged regardiess of the state of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. data input/output pins. the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allow- ing inpu t data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dqs0~dqs7 the data strobes, associated with one data byte, source d with data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode, the data strobe is sourced by the ddr2 sdrams and is sent at the leading edge of the data window. dqs signals are com- plements, and timing is relative to the crosspoint of respective dqs and dqs if the module is to be oper- ated in single ended strobe mode, all dqs signals must be tied on the system board to v ss and ddr2 sdram mode registers programmed appropriately. power supplies for core, i/o, serial pr esence detect, and ground for the module. sda in/out this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resistor must be con- nected to v dd to act as a pull up. scl input this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from scl to v dd to act as a pull up. address pins used to select the seri al presence detect base address. the test pin is reserved for bus analysis tools and is n ot connected on normal memory modules(so- dimms). h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 7 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 7. functional block diagram : 7.1 512mb, 64mx64 module - m470t6464fbs (populated as 1 rank of x16 ddr2 sdrams) s 0 dqs1 dqs 1 dm1 cs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 ldqs ldqs ldm dqs0 dqs 0 dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs5 dqs 5 dm5 cs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 ldqs ldqs ldm dqs4 dqs 4 dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs3 dqs 3 dm3 cs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 ldqs ldqs ldm dqs2 dqs 2 dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs7 dqs 7 dm7 cs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 ldqs ldqs ldm dqs6 dqs 6 dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm o d t c k e o d t c k e o d t c k e o d t c k e odt0 cke0 spd sa0 scl sda v ss ddr2 sdrams d0 - d3, spd v ref ddr2 sdrams d0 - d3 ddr2 sdrams d0 - d3, v dd and v ddq v dd v ddspd serial pd wp sa1 scl a0 a1 a2 a0 - a13 ddr2 sdrams d0 - d3 ras ddr2 sdrams d0 - d3 cas ddr2 sdrams d0 - d3 we ddr2 sdrams d0 - d3 ba0 - ba2 ddr2 sdrams d0 - d3 3 ? + 5% note : 1. dq, dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras, cas, we resistors : 3.0 ohms 5%. * wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 2 ddr2 sdrams 2 ddr2 sdrams 3 ? + 5% h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 8 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 7.2 1gb, 128mx64 module - m470t2863fb3 (populated as 1 rank of x8 ddr2 sdrams) cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs dqs dm dqs0 dqs 0 dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 s 0 odt0 cke0 3 ? + 5% odt cke cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs dqs dm dqs1 dqs 1 dm1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 odt cke cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs dqs dm dqs2 dqs 2 dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 odt cke cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs dqs dm dqs3 dqs 3 dm3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 odt cke cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs dqs dm dqs4 dqs 4 dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 odt cke cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs dqs dm dqs5 dqs 5 dm5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 odt cke cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs dqs dm dqs6 dqs 6 dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 odt cke cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dqs dqs dm dqs7 dqs 7 dm7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 odt cke s1 odt1 cke1 n.c. n.c. n.c. spd sa0 scl sda v ss ddr2 sdrams d0 - d7, spd v ref ddr2 sdrams d0 - d7 ddr2 sdrams d0 - d7, v dd and v ddq v dd v ddspd serial pd wp sa1 scl a0 a1 a2 a0 - a13 ddr2 sdrams d0 - d7 ras ddr2 sdrams d0 - d7 cas ddr2 sdrams d0 - d7 we ddr2 sdrams d0 - d7 ba0 - ba2 ddr2 sdrams d0 - d7 3 ? + 5% note : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 3.0 ohms 5%. * wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 4 ddr2 sdrams 4 ddr2 sdrams h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 9 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 7.3 1gb, 128mx64 module - M470T2864FB3 (populated as 2 ranks of x16 ddr2 sdrams) s 0 dqs1 dqs 1 dm1 cs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 ldqs ldqs ldm dqs0 dqs 0 dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs5 dqs 5 dm5 cs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 ldqs ldqs ldm dqs4 dqs 4 dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs3 dqs 3 dm3 cs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 ldqs ldqs ldm dqs2 dqs 2 dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs7 dqs 7 dm7 cs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 ldqs ldqs ldm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm c k e o d t c k e o d t c k e o d t c k e o d t cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 ldqs ldqs ldm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 ldqs ldqs ldm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm c k e o d t c k e o d t cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 ldqs ldqs ldm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 ldqs ldqs ldm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm c k e o d t c k e o d t s 1 cke0 cke1 odt0 odt1 spd sa0 scl sda v ss ddr2 sdrams d0 - d7, spd v ref ddr2 sdrams d0 - d7 ddr2 sdrams d0 - d7, v dd and v ddq v dd v ddspd serial pd wp sa1 scl a0 a1 a2 a0 - a13 ddr2 sdrams d0 - d7 ras ddr2 sdrams d0 - d7 cas ddr2 sdrams d0 - d7 we ddr2 sdrams d0 - d7 ba0 - ba2 ddr2 sdrams d0 - d7 3 ? + 5% note : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 3.0 ohms 5%. * wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 4 ddr2 sdrams 4 ddr2 sdrams 3 ? + 5% dqs6 dqs 6 dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 10 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 7.4 2gb, 256mx64 module - m470t5663fb3 (populated as 2 ranks of x8 ddr2 sdrams) odt0 cke0 s 1 odt1 cke1 spd sa0 scl sda v ss ddr2 sdrams d0 - d15, spd v ref ddr2 sdrams d0 - d15 ddr2 sdrams d0 - d15, v dd and v ddq v dd v ddspd serial pd wp sa1 scl a0 a1 a2 a0 - a13 ddr2 sdrams d0 - d15 ras ddr2 sdrams d0 - d15 cas ddr2 sdrams d0 - d15 we ddr2 sdrams d0 - d15 ba0 - ba2 ddr2 sdrams d0 - d15 10 ? + 5% 3 ? + 5% s 0 dqs1 dqs 1 dm1 cs 0 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs dqs dm dqs0 dqs 0 dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm dqs5 dqs 5 dm5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs dqs dm dqs4 dqs 4 dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm dqs3 dqs 3 dm3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs dm dqs2 dqs 2 dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm dqs7 dqs 7 dm7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs dm dqs6 dqs 6 dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm o d t 0 c k e 0 cs 1 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dqs dqs dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm o d t 1 c k e 1 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dqs dqs dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs dm cs 0 o d t 0 c k e 0 cs 1 o d t 1 c k e 1 cs 0 d1 d5 o d t 0 c k e 0 cs 1 d9 o d t 1 c k e 1 d13 cs 0 o d t 0 c k e 0 cs 1 o d t 1 c k e 1 cs 0 d2 d6 o d t 0 c k e 0 cs 1 d10 o d t 1 c k e 1 d14 cs 0 o d t 0 c k e 0 cs 1 o d t 1 c k e 1 cs 0 d3 d7 o d t 0 c k e 0 cs 1 d11 o d t 1 c k e 1 d15 cs 0 o d t 0 c k e 0 cs 1 o d t 1 c k e 1 note : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 10.0 ohms 5%. * wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 8 ddr2 sdrams 8 ddr2 sdrams h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 11 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 8. absolute maximum dc ratings note : 1. stresses greater than those listed under ?absolute maximum ra t ings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions a bove those indicated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the cente r/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. 9. ac & dc operating conditions 9.1 recommended dc operating conditions (sstl - 1.8) note : there is no specific device v dd supply voltage requirement for sstl-1.8 compliance. however under all conditions v ddq must be less than or equal to v dd . 1. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 2. peak to peak ac noise on v ref may not exceed +/-2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. ac parameters are measured with v dd , v ddq and v ddl tied together. 5. sodimms that include an optional temperature sensor may require a restricted v ddspd operating voltage range for proper operation of the temperature sensor. refer to the thermal sensor specification fo r details regarding the supported voltage range. all other functions of the sodimm spd are supported across the full v ddspd range. symbol parameter rating units note v dd voltage on v dd pin relative to v ss - 1.0 v ~ 2.3 v v 1 v ddq voltage on v ddq pin relative to v ss - 0.5 v ~ 2.3 v v 1 v ddl voltage on v ddl pin relative to v ss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to v ss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1, 2 symbol parameter rating units note min. typ. max. v dd supply voltage 1.7 1.8 1.9 v v ddl supply voltage for dll 1.7 1.8 1.9 v 4 v ddq supply voltage for output 1.7 1.8 1.9 v 4 v ref input reference voltage 0.49*v ddq 0.50*v ddq 0.51*v ddq mv 1,2 v tt termination voltage v ref -0.04 v ref v ref +0.04 v 3 symbol parameter rating units note min. max. v ddspd core supply voltage 1.7 3.6 v 5 h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 12 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 9.2 operating temperature condition note : 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ea se refer to jesd51.2 standard. 2. at 85 - 95 c ope rat ion temperature range, doubling refresh commands in frequen cy to a 32ms period ( trefi=3. 9 us ) is required, and to ent er to self refresh mode at this temperature range, an emrs command is required to change internal refresh rate. 9.3 input dc logic level 9.4 input ac logic level 9.5 ac input test conditions note : 1. input waveform timing is referenced to the input signal crossing through the v ih/il (ac) level applied to the device under test. figure 1. ac input test signal waveform 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. symbol parameter rating units note t oper operating temperature 0 to 95 c 1, 2 symbol parameter min. max. units note v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter ddr2-667/800 units min. max. v ih (ac) ac input logic high v ref + 0.200 v v il (ac) ac input logic low v ref - 0.200 v symbol condition value units note v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 13 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 10. idd specification parameters definition (idd values are for full operating range of voltage and temperature) symbol proposed conditions units note idd0 operating one bank active-precharge current ; tck = tck(idd), trc = trc(idd), tras = trasmin(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), trc = trc (idd), tras = trasmin(idd), trcd = trcd(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle; tck = tck(idd); cke is low; other cont rol and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; tck = tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl (idd), al = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; addr ess bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), tras = tras- max(idd), trp = trp(idd); cke is high, cs is high between valid commands; address bus inputs are switch- ing; data pattern is same as idd4w ma idd5b burst auto refresh current ; tck = tck(idd); refresh command at every trfc(idd) interval; cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal ma low power ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl (idd), al = trcd(idd)-1*tck(idd); tck = tck(idd), trc = trc(idd), trrd = trrd(idd), tfaw = tfaw(idd), trcd = 1*tck(idd); cke is high, cs is high between valid com- mands; address bus inputs are stable during deselects; data pattern is same as idd4r; refer to the following page for detailed timing conditions ma h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 14 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 11. operating current table : 11.1 m470t6464fbs : 64mx64 512mb module ( ta=0 o c , v dd = 1.9v) note : module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. 11.2 m470t2863fb3 : 128mx64 1gb module (ta=0 o c, v dd = 1.9v) note : module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. operating current table : symbol 800@cl=5 800@cl=6 667@cl=5 units note ce7 cf7 ce6 idd0 220 220 200 ma idd1 260 260 240 ma idd2p 40 40 40 ma idd2q 88 88 88 ma idd2n 116 116 108 ma idd3p-f 100 100 96 ma idd3p-s 80 80 80 ma idd3n 160 160 148 ma idd4w 380 380 360 ma idd4r 420 420 380 ma idd5 440 440 420 ma idd6 40 40 40 ma idd7 720 720 660 ma symbol 800@cl=5 800@cl=6 667@cl=5 units note ce7 cf7 ce6 idd0 360 360 344 ma idd1 408 408 384 ma idd2p 80 80 80 ma idd2q 160 160 160 ma idd2n 200 200 192 ma idd3p-f 184 184 176 ma idd3p-s 160 160 160 ma idd3n 296 296 280 ma idd4w 576 576 520 ma idd4r 640 640 560 ma idd5 840 840 800 ma idd6 80 80 80 ma idd7 1280 1280 1160 ma h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 15 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 11.3 M470T2864FB3 : 128mx64 1gb module ( ta=0 o c , v dd = 1.9v) note : module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. 11.4 m470t5663fb3 : 256mx64 2gb module (ta=0 o c, v dd = 1.9v) note : module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol 800@cl=5 800@cl=6 667@cl=5 units note ce7 cf7 ce6 idd0 336 336 308 ma idd1 376 376 348 ma idd2p 80 80 80 ma idd2q 176 176 176 ma idd2n 232 232 216 ma idd3p-f 200 200 192 ma idd3p-s 160 160 160 ma idd3n 276 276 256 ma idd4w 496 496 468 ma idd4r 536 536 488 ma idd5 556 556 528 ma idd6 80 80 80 ma idd7 836 836 768 ma symbol 800@cl=5 800@cl=6 667@cl=5 units note ce7 cf7 ce6 idd0 560 560 536 ma idd1 608 608 576 ma idd2p 160 160 160 ma idd2q 320 320 320 ma idd2n 400 400 384 ma idd3p-f 368 368 352 ma idd3p-s 320 320 320 ma idd3n 496 496 472 ma idd4w 776 776 712 ma idd4r 840 840 752 ma idd5 1040 1040 992 ma idd6 160 160 160 ma idd7 1480 1480 1352 ma h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 16 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 12. input/output capacitance (v dd =1.8v, v ddq =1.8v, ta=25 o c) note : dm is internally loaded to match dq and dqs identically. 13. electrical characteristics & ac timing for ddr2-800/667 (0 c < t oper < 95 c; v ddq = 1.8v + 0.1v; v dd = 1.8v + 0.1v) 13.1 refresh parameters by device density 13.2 speed bins and cl, trcd, trp, trc and tras for corresponding bin speed ddr2-800(e7) ddr2-800(f7) ddr2-667(e6) units bin (cl - trcd - trp) 5 - 5 - 5 6 - 6- 6 5 - 5 - 5 parameter min max min max min max tck, cl=3 5 8 - - 5 8 ns tck, cl=4 3.75 8 3.75 8 3.75 8 ns tck, cl=5 2.5 8 3 8 3 8 ns tck, cl=6 - - 2.5 8 - - ns trcd 12.5 - 15 - 15 - ns trp 12.5 - 15 - 15 - ns trc 57.5 - 60 - 60 - ns tras 45 70000 45 70000 45 70000 ns parameter symbol min max units non-ecc m470t6464fbs input capacitance, ck and ck cck - 24 pf input capacitance, cke , cs , addr, ras , cas , we ci - 34 input/output capacitance, dq, dm, dqs, dqs cio(667/800) - 5.5 non-ecc symbol m470t2863fb3 units input capacitance, ck and ck cck - 32 pf input capacitance, cke , cs , addr, ras , cas , we ci - 42 input/output capacitance, dq, dm, dqs, dqs cio(667/800) - 5.5 non-ecc symbol M470T2864FB3 units input capacitance, ck and ck cck - 32 pf input capacitance, cke , cs , addr, ras , cas , we ci - 34 input/output capacitance, dq, dm, dqs, dqs cio(667/800) - 9 non-ecc symbol m470t5663fb3 units input capacitance, ck and ck cck - 48 pf input capacitance, cke , cs , addr, ras , cas , we ci - 42 input/output capacitance, dq, dm, dqs, dqs cio(667/800) - 9 parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/refresh command time trfc 75 105 127.5 195 327.5 ns average periodic refresh interval trefi 0 c t case 85c 7.8 7.8 7.8 7.8 7.8 s 85 c < t case 95c 3.9 3.9 3.9 3.9 3.9 s h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 17 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 13.3 timing parameters by speed grade (refer to notes for informations related to this table at the component datasheet) parameter symbol ddr2-800 ddr2-667 units note min max min max dq output access time from ck/ck tac -400 400 - 450 450 ps 40 dqs output access time from ck/ck tdqsck -350 350 - 400 400 ps 40 average clock high pulse width tch(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 average clock low pulse width tcl(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 ck half pulse period thp min(tcl(abs), tch(abs)) x min(tcl(abs), tch(abs)) x ps 37 average clock period tck(avg) 2500 8000 3000 8000 ps 35,36 dq and dm input hold time tdh(base) 125 x 175 x ps 6,7,8,21,28,31 dq and dm input setup time tds(base) 50 x 100 x ps 6,7,8,20,28,31 control & address input pulse width for each input tipw 0.6 x 0.6 x tck(avg) dq and dm input pulse width for each input tdipw 0.35 x 0.35 x tck(avg) data-out high-impedance time from ck/ck thz x tac(max) x tac(max) ps 18,40 dqs/dqs low-impedance time from ck/ck tlz(dqs) tac(min) tac(max) tac(min) tac(max) ps 18,40 dq low-impedance time from ck/ck tlz(dq) 2* tac(min) tac(max) 2* tac(min) tac(max) ps 18,40 dqs-dq skew for dqs and associated dq signals tdqsq x 200 x 240 ps 13 dq hold skew factor tqhs x 300 x 340 ps 38 dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x ps 39 dqs latching rising transitions to associated clock edges tdqss - 0.25 0.25 -0.25 0.25 tck(avg) 30 dqs input high pulse width tdqsh 0.35 x 0.35 x tck(avg) dqs input low pulse width tdqsl 0.35 x 0.35 x tck(avg) dqs falling edge to ck setup time tdss 0.2 x 0.2 x tck(avg) 30 dqs falling edge hold time from ck tdsh 0.2 x 0.2 x tck(avg) 30 mode register set command cycle time tmrd 2 x 2 x nck mrs command to odt update delay tmod 0 12 0 12 ns 32 write postamble twpst 0.4 0.6 0.4 0.6 tck(avg) 10 write preamble twpre 0.35 x 0.35 x tck(avg) address and control input hold time tih(base) 250 x 275 x ps 5,7,9,23,29 address and control input setup time tis(base) 175 x 200 x ps 5,7,9,22,29 read preamble trpre 0.9 1.1 0.9 1.1 tck(avg) 19,41 read postamble trpst 0.4 0.6 0.4 0.6 tck(avg) 19,42 activate to activate command period for 1kb page size products trrd 7.5 x 7.5 x ns 4,32 activate to activate command period for 2kb page size products trrd 10 x 10 x ns 4,32 h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 18 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm parameter symbol ddr2-800 ddr2-667 units note min max min max four activate window for 1kb page size products tfaw 35 x 37.5 x ns 32 four activate window for 2kb page size products tfaw 45 x 50 x ns 32 cas to cas command delay tccd 2 x 2 x nck write recovery time twr 15 x 15 x ns 32 auto precharge write recovery + precharge time tdal wr + tnrp x wr + tnrp x nck 33 internal write to read command delay twtr 7.5 x7 . 5 x ns 24,32 internal read to precharge command delay trtp 7.5 x 7.5 x ns 3,32 exit self refresh to a non-read command txsnr trfc + 10 xtrfc + 10 x ns 32 exit self refresh to a read command txsrd 200 x2 0 0 x nck exit precharge power down to any command txp 2 x 2 x nck exit active power down to read command txard 2 x 2 x nck 1 exit active power down to read command (slow exit, lower power) txards 8 - al x 7 - al x nck 1,2 cke minimum pulse width (high and low pulse width) tcke 3 x 3 x nck 27 odt turn-on delay taond 2 2 2 2 nck 16 odt turn-on taon tac(min) tac(max)+0.7 tac(min) tac(max)+0.7 ns 6,16,40 odt turn-on (power-down mode) taonpd tac(min)+2 2*tck(avg) +tac(max)+1 tac(min)+2 2*tck(avg) +tac(max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 nck 17,45 odt turn-off taof tac(min) tac(max)+0.6 tac(min) tac(max)+0.6 ns 17,43,45 odt turn-off (power-down mode) taofpd tac(min)+2 2.5*tck(avg)+ tac(max)+1 tac(min)+2 2.5*tck(avg)+ tac(max)+1 ns odt to power down entry latency tanpd 3 x3 x nck odt power down exit latency taxpd 8 x8 x nck ocd drive mode output delay toit 0 12 0 12 ns 32 minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck(avg) +tih x tis+tck(avg) +tih xn s1 5 h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 19 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 14. physical dimensions : 14.1 64mbx16 based 64mx64 module (1rank) - m470t6464fbs the used device is 64m x16 ddr2 sdram, flip-chip. ddr2 sdram part no : k4t1g164qf units : millimeters 67.60 0.15 mm 4.00 0.10 20.00 0.15 mm 30.00 0.15 mm 1 199 11.40 0.15 mm 47.40 0.15 mm 6.00 0.15 mm spd a 63.00 0.15 mm 16.25 0.15 mm min 2.00 67.60 0.15 mm 30.00 0.15 mm 2 200 a b 4.20 0.15 2.70 0.10 4.00 0.10 1.0 0.05 1.50 0.10 front side 4.20 0.15 1.80 0.10 4.00 0.10 1.0 0.05 2.40 0.10 back side 0.60 0.15 0.45 0.03 2.55 0.15 0.20 0.15 detail a detail b 3.8 mm max 1.1 mm max h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 20 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 14.2 128mbx8 based 128mx64 module (1rank) - m470t2863fb3 the used device is 128m x8 ddr2 sdram, flip-chip ddr2 sdram part no : k4t1g084qf units : millimeters 67.60 0.15 mm 4.00 0.10 20.00 0.15 mm 30.00 0.15 mm 1 199 11.40 0.15 mm 47.40 0.15 mm 6.00 0.15 mm spd 3.8 mm max 1.1 mm max a 63.00 0.15 mm 16.25 0.15 mm min 2.00 67.60 0.15 mm 30.00 0.15 mm 22 0 0 4.20 0.15 2.70 0.10 4.00 0.10 1.0 0.05 1.50 0.10 front side 4.20 0.15 1.80 0.10 4.00 0.10 1.0 0.05 2.40 0.10 back side 0.60 0.15 0.45 0.03 2.55 0.15 0.20 0.15 detail a detail b a b h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 21 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 14.3 64mbx16 based 128 mx64 module (2ranks) - M470T2864FB3 the used device is 64m x 16 ddr2 sdram, flip-chip. ddr2 sdram part no : k4t1g164qf 67.60 0.15 mm 4.00 0.10 20.00 0.15 mm 30.00 0.15 mm 1 199 11.40 0.15 mm 47.40 0.15 mm 6.00 0.15 mm spd 3.8 mm max 1.1 mm max a 63.00 0.15 mm 16.25 0.15 mm min 2.00 67.60 0.15 mm 30.00 0.15 mm 2 200 4.20 0.15 2.70 0.10 4.00 0.10 1.0 0.05 1.50 0.10 front side 4.20 0.15 1.80 0.10 4.00 0.10 1.0 0.05 2.40 0.10 back side 0.60 0.15 0.45 0.03 2.55 0.15 0.20 0.15 detail a detail b a b units : millimeters h t t p : / / w w w . b d t i c . c o m / s a m s u n g - 22 - datasheet ddr2 sdram rev. 1.2 unbuffered sodimm 14.4 128mbx8 based 256mx64 module (2ranks) - m470t5663fb3 the used device is 128m x8 ddr2 sdram, flip-chip ddr2 sdram part no : k4t1g084qf units : millimeters 3.8 mm 1.1mm max max 67.60 0.15 mm 4.00 0.10 20.00 0.15 mm 30.00 0.15 mm 1 199 11.40 0.15 mm 47.40 0.15 mm 6.00 0.15 mm 63.00 0.15 mm 16.25 0.15 mm min 2.00 67.60 0.15 mm 30.00 0.15 mm 2 200 spd a b a 4.20 0.15 2.70 0.10 4.00 0.10 1.0 0.05 1.50 0.10 front side 4.20 0.15 1.80 0.10 4.00 0.10 1.0 0.05 2.40 0.10 back side 0.60 0.15 0.45 0.03 2.55 0.15 0.20 0.15 detail a detail b h t t p : / / w w w . b d t i c . c o m / s a m s u n g |
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